Job Responsibilities

• Work experience with node 16nm, 14nm, 10nm, 7nm, 5nm, etc
• Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification,etc.
• Well versed with Cadence or Synopsys tools is must.
• Experience with Static Timing Analysis in Primetime or Primetime-SI is must.
• Hands-on experience in scripting languages such as PERL, TCL,etc.
• Timing closure on high-speed interfaces is a plus
• Knowledge on Full chip Physical Design is added advantage