Job Responsibilities

• He/she is responsible for micro-architecture design and development of CPU Subsystem or associated component IP like high performance Bus Architectures, Memory Controllers/ DDR/USB/ NVMe/PCIE interface etc.
• Micro-architecture development and implementation of complex IP and/or ASIC block, logic designs, and HDL code for IP/ASIC blocks.
• Working individually and sometimes leading other team members in delivery of RTL design for product features.
• Strong RTL design experience of IP designs for microcontrollers/ Microprocessors expected.
• Experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC, LEC
• Knowledge & experience of building on chip bus infrastructure using AHB or AXI based IPs/ Blocks

Job Responsibilities

• Work experience with node 16nm, 14nm, 10nm, 7nm, 5nm, etc
• Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification,etc.
• Well versed with Cadence or Synopsys tools is must.
• Experience with Static Timing Analysis in Primetime or Primetime-SI is must.
• Hands-on experience in scripting languages such as PERL, TCL,etc.
• Timing closure on high-speed interfaces is a plus
• Knowledge on Full chip Physical Design is added advantage

Job Responsibilities

• Custom Layout Design to execute Chip, Block, and sub-block level from circuit schematics.
• Independent Handling and Layout Design of various Analog and Mixed Signal blocks and sub-blocks of PLLs, CDRs, SerDes, LVDS, HDMI, Serial I/Os, and Other Analog Blocks like Switched Capacitor Circuits, Operational amplifiers, Comparators, Oscillators, Voltage and Current Reference circuits etc.
• Work independently, collaborating with Project Leader and design engineers.
• Responsible for the timely execution as well as overall physical design quality of the implemented circuits.
• Follow the Project Execution Plan, Project Schedule, Work Assignment and EDA tool usage plan. – Active Participation in Customer Project Reviews.
• Layout Design in technologies with feature size 0.18um, 150nm, 90nm, 65nm, 40nm CMOS, BiCMOS, SOI Process etc.

Job Responsibilities

• Experience in SOC/IP/ASIC/GLS Functional Verification
• He/she will be involved in developing testbench for the block/cluster, testcases, test plans and functional and code coverage.
• Knowledge of Industry standard protocols –Ethernet, PCIE, USB, DRR3/4, AXI, AHB and low speed peripherals, etc.
• Knowledge of Clocking, Boot/Reset flows.
• Experience with System Verilog/OVM/UVM SOC development environment is must
• Experience with Low power/UPF verification techniques.
• Strong background in scripting – PERL, TCL, Python.
• Understanding of software and/or hardware validation techniques