Digital ASIC/ SoC
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Digital ASIC/ SoC
RTL to Netlist
- RTL Design Expertise
- Integration , Directed TB Support
- Micro Arch Development Support
- RDC/CDC Lint Signoff
- Synthesis, Equivalence check, GLS Signoff
implementation Flows
- Placement Floorplanning & Routing
- CTS, RNS & Parasitic Extraction
- DFT
- STA
- DRC, LVS
- Back Annotation
- Post Layout Simulation
TapeOut
SPEC-In
Review
Approval
- Chip / System Specification
- SoC Architecture Definition
- IP Identification
SOC/IP Design
SOC/IP Verification
Design Tool Signoff
- RTL Chip Top Design
- IP Sub System Design
- Design Verification
- SDC/RDC/CDC Lint Check
SoC Prototyping
SoC Validation
Emulation
- FPGA Programming
- FPGA Verification
- FPGA Emulation
SW Prototyping
Driver Development
Boot Sequence generation
- Drivers
- BSP
- Linux
- Android, U-Boot
- Middle-Wares
System Prototyping
- EVB Design
- System Bring Up
- Test Chip
- Validation
Functional Verification
- High-Speed Protocol Verif Expertise
- IP/Verification IP Test Plan Execution
- SVA (Assertions)
- Coverage Improvement
- Debug Support
Emulation
- Software Development
- Hardware/Software Co-simulation
- Application/System Level Validation
- Emulation Test Suite with better test coverage
- Debug Support
Power Profiling
- Power Budgeting
- Power Optimization
- Profile for Power Sign-off and Package Design
Formal Verification
- Bug Hunting using advanced Formal techniques
- Expertise in Jasper, VC formal and other formal tools
- RTL analysis, property checking, sequential equivalency checking and X-propagation analysis